1. Field of the Invention
This invention relates generally to semiconductors and especially to self-aligned lateral bipolar transistors of narrow base width and methods for manufacturing such transistors, particularly in integrated circuit structures containing vertical bipolar transistors of opposite polarity.
2. Description of the Prior Art
Lateral bipolar transistors are of substantial importance in semiconductor devices. Unlike vertical bipolar transistors in which base width can be accurately regulated by controlling vertical diffusions, lateral transistors pose greater difficulties in producing bases which are sufficiently narrow to achieve high gain and whose dimensions are accurately controllable and reproducible.
Within the prior art, R. Schinella et al. disclose the structure and method for making a lateral transistor using two diffusions through a single mask opening in U.S. Pat. No. 3,873,989, "Double-Diffused, Lateral Transistor Structure," U.S. Pat. No. 3,919,005, "Method for Fabricating Double-Diffused, Lateral Transistor," and U.S. Pat. No. 3,945,857, "Method for Fabricating Double-Diffused, Lateral Transistors." A lateral transistor made according to the foregoing patents typically has a minimum base width of approximately 0.5 to 1 micron with an impurity gradient in the horizontal direction across the base; this impurity gradient is undersirable in some applications.
D. O'Brien discloses a method for fabricating a singly-diffused lateral transistor in U.S. Pat. No. 4,066,473, "Method of Fabricating High-Gain Transistors." The base width of the lateral transistor manufactured according to this O'Brien patent is typically 1-3 microns using current masking technology. There is substantially no horizontal impurity gradient across the base.
Bipolar transistors of both the lateral and vertical type often utilize oxide-isolation techniques such as those disclosed by D. Peltzer in U.S. Pat. No. 3,648,125, "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure," to demarcate the active semiconductor regions. Such oxide-isolation techniques are further described by Peltzer in "Isoplanar Processing," 1972 Wescon Technical Papers, presented at Western Electronic Show and Convention, Sept. 19-22, 1972, Session 19, Section 19/2, pages 1-4. D. O'Brien discloses the use of an anti-inversion region with oxide isolation for making complementary lateral and vertical transistors in U.S. Pat. No. 3,962,717, "Oxide Isolated Integrated Injection Logic with Selective Guard Ring," and U.S. Pat. No. 3,993,513, "Combined Method for Fabricating Oxide-Isolated Vertical Bipolar Transistors and Complementary Oxide-Isolated Lateral Bipolar Transistors and the Resulting Structures."
In fabricating integrated circuit structures such as those having complementary lateral and vertical bipolar transistors, many of the semiconductor regions may be formed by ion implantation techniques. One of the perennial problems in ion implantation is the prevention of ions in the ion beam from entering semiconductor regions where implantation is not desired. J. Stephen in "The Contribution of Ion Implantation to Silicon Device Technology," Proceedings of the Technical Program, International Microelectronics Conference, Anaheim, Calif. Feb. 11-13 and June 17-19 1975, pages 88-97, suggests that silicon nitride might be used as a mask to prevent undesired ion implantation in semiconductor circuits.